1. Field of the Invention
The present invention is related to a design layout generating method, and more particularly, to a design layout generating method for weak pattern management.
2. Description of the Prior Art
As known, it takes multiple stages to fabricate an integrated circuit product from the beginning of designing the integrated circuit. Generally, some defects are possibly generated in any of the multiple stages. If the defect is found after the integrated circuit product is fabricated, it is necessary to identify the source of problems from the beginning. Under this circumstance, the speed of launching the product will be slowed down.
For solving these drawbacks, a simple rule (e.g. a minimum critical dimension) or a physical model is conventionally used in the circuit design layout in order to sieve out the area that is unable to tolerate the process variation. In such way, the weak patterns prone to error in mass production can be identified in the earlier stages. After the weak patterns are identified, the technician may try to improve the production process and eliminate the possible product weakness in the earlier stages. However, since the conventional method lacks systematical and hierarchical analyses, the estimated weak patterns are far from the real electrical performance of the product. Under this circumstance, the product yield is usually unsatisfied. Therefore, there is a need of providing an integrated circuit design and fabrication method in order to obviate the drawbacks encountered from the prior art.